Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL

Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL
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Modeling, Synthesis, and Rapid Prototyping with the VERILOG (TM) HDL

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by Michael D. Ciletti

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This product is a selection from the Xilinx Design Series.

Back Cover

Designers facing the challenge of the next millennium must have the tools to exploit the rapidly advancing technology of cell-based and other ASIC device technologies, such as Field-Programmable Gate Arrays (FPGAs). It is clear that the leverage offered to designers by hardware description languages will continue to shape design methodologies at all levels of integration, from Programmable Logic Devices (PLDs) to... read more



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